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In the datasheet, the maximum clock frequency (when the ADC is powered with maximum voltage of 5V) is 3.6 MHz. Each read takes about 24 clock cycles which gives us a maximum sampling rate of about 150 KSPS. However, I have a couple of questions:

1) Why is it that the ADC is advertised to be a 200 ksps ADC when the theoretical maximum is about 150 KSPS?

2) Is the calculation that I have done correct?

Thank you!

Always Learning Forever
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1 Answers1

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You have made the assumption that 24 clocks are required. A quick look at the datasheet suggests 18 clocks are required per cycle. This gives a figure of 3600000 / 18 = 200000

The faulty assumption is that all devices require transfers in multiples of 8 bits.

joan
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